What Is Backside Power Delivery? Why Intel and TSMC Chips Need It

Backside power delivery is a chipmaking technique that moves a processor's power wiring from the front of the silicon wafer, where it has always lived alongside signal wiring, to the back. Separating the two frees up crowded front-side space for the wires that actually move data, and it shortens the path power has to travel to reach each transistor, cutting resistance and voltage loss along the way. Intel calls its version PowerVia, and it is already running inside Intel's Core Ultra Series 3 "Panther Lake" laptop chips and Xeon 6+ "Clearwater Forest" server chips. TSMC's version, called Super Power Rail, is the headline feature of its upcoming A16 node, targeted for production later in 2026.

Why the Front of the Chip Was Running Out of Room

Every modern processor is built up in layers on top of a silicon wafer. The transistors themselves sit at the bottom of that stack, and above them runs a dense mesh of metal wiring, built in a process called the back-end-of-line, or BEOL. Historically, that single stack of metal layers has had to do two jobs at once: carry the signals that move data between transistors, and carry the power and ground lines that keep every transistor supplied with voltage.

As transistors have shrunk generation after generation, that shared stack has become a genuine bottleneck. Power and ground lines need to be relatively wide and low-resistance to avoid wasting energy as heat, while signal wires benefit from being as thin and densely packed as possible. Cramming both into the same handful of front-side metal layers means one job compromises the other: either power delivery gets squeezed into thinner wires than it would like, which increases resistance and voltage droop, or signal routing gets pushed around power lines, which adds congestion and can force a less efficient, larger chip layout.

The industry's term for the first problem is IR drop: the voltage that arrives at a given transistor is lower than the voltage supplied at the chip's power pins, because every bit of resistance in the wire between them eats a little of it. On a modern design with billions of transistors switching billions of times a second, that lost voltage translates directly into wasted power and a ceiling on how fast the chip can reliably run.

What Backside Power Delivery Actually Moves

Backside power delivery, often abbreviated BSPDN for "backside power delivery network," solves this by giving power its own, separate stack of wiring on the opposite side of the wafer from the signal layers. Instead of competing with signal wires for the same front-side metal layers, the power-delivery network is built into a handful of thick, low-resistance metal layers on the back of the chip, with short vertical connections reaching through the thinned silicon to feed each transistor.

The front side is then left almost entirely to the business of moving signals around, which chipmakers say lets them use fewer, better-optimized metal layers up top and pack standard logic cells more tightly, since those cells no longer need to leave room for wide power rails running past them.

How It Physically Works, in Plain Terms

The exact process details are proprietary to each chipmaker, but the broad sequence described by semiconductor researchers at imec, an independent nanoelectronics research institute that has published some of the most detailed public work on the technique, follows roughly this path:

• Build the front side first. Transistors and the first layer or two of front-side metal wiring are built normally, on top of the base silicon wafer.
• Flip and bond. The wafer is flipped upside down and bonded, front-side down, to a second "carrier" wafer, which holds everything in place for the next steps.
• Thin the back way down. With the finished front side now protected underneath, the original wafer's backside silicon is ground and etched away until only a few hundred nanometers of silicon remain above the transistors, thin enough to expose the bottom of the devices from the back.
• Drill tiny vias. Nanoscale through-silicon vias, or nano-TSVs, are etched from the newly exposed backside down to the transistor layer and filled with metal (commonly tungsten), creating a vertical electrical connection from back to front.
• Build the backside power grid. New metal layers are deposited on this thinned backside, forming the power-delivery network itself, which connects down through the nano-TSVs to feed each transistor or group of cells directly.

Imec's published research notes that this adds real manufacturing complexity: wafer bonding, precision thinning, and etching via holes with very high aspect ratios all have to be done without damaging transistors that, by this point, are already fully formed. Imec also found that moving power to the backside doesn't come for free on the device side either; in its test structures, carrier mobility shifted slightly for both PMOS and NMOS transistors after backside processing, in different directions, which is the kind of detail that keeps backside power delivery a genuinely hard engineering problem rather than a simple wiring swap.

Intel's PowerVia: What It Is and Which Chips Actually Use It

Intel's implementation is called PowerVia, and it is one of two headline features of the Intel 18A process node, alongside RibbonFET, Intel's first new transistor architecture in more than a decade (a gate-all-around design, where the transistor's gate wraps fully around the channel instead of just three sides, as in older FinFET transistors). Intel describes 18A as the first high-volume process, anywhere in the industry, to combine gate-all-around transistors with backside power delivery in the same node.

According to Intel's own foundry materials, moving coarse-pitch power wiring and bump connections to the backside of the die, along with embedding nano-scale through-silicon vias in each standard cell for power distribution, is meant to relieve the routing congestion that mixed power-and-signal wiring causes as density rises. Intel's published figures for 18A, compared with its prior Intel 3 node, include up to 15% better performance per watt and roughly 30% better chip density; separate PowerVia-specific claims cite up to 10 times lower worst-case dynamic voltage droop and up to 11% tighter block-level area.

On the product side, Intel has now shipped two 18A chips that use PowerVia:

• Panther Lake (marketed as Core Ultra Series 3) is Intel's first client processor built on 18A. Intel previewed its architecture on October 9, 2025, formally launched it at CES in early January 2026, and began global retail availability on January 27, 2026.
• Clearwater Forest (marketed as Xeon 6+) is Intel's first data-center processor on 18A, with compute tiles fabricated on 18A stacked over base tiles on the older Intel 3 node using Intel's advanced packaging. Intel previewed it alongside Panther Lake in October 2025 and launched it around Computex in roughly June 2026.

Intel has also described follow-on variants of the node: 18A-P, a second-generation version of RibbonFET and PowerVia aimed at further performance-per-watt gains, and 18A-PT, which Intel bills as the industry's first base die with backside power delivery built specifically for advanced 3D chip stacking.

Panther Lake and Clearwater Forest at a Glance

Those dates matter because they settle a distinction that's easy to blur: Intel's October 2025 event was a preview of upcoming architecture, not a shipping announcement. The chips that actually reached customers carrying PowerVia inside them arrived months later, in 2026.

TSMC's Super Power Rail and the A16 Node

TSMC's competing approach is called Super Power Rail, and it's the flagship feature of the company's A16 process, a 1.6-nanometer-class node that pairs Super Power Rail with TSMC's nanosheet transistors (TSMC's own gate-all-around design). TSMC unveiled A16 at its North America Technology Symposium on April 24, 2024, describing it as a backside power rail solution meant to free up front-side routing resources for signals, the same basic rationale behind Intel's PowerVia.

TSMC's own published figures compare A16 against its N2P node: an 8-10% speed improvement at the same supply voltage, a 15-20% power reduction at the same speed, and up to roughly 1.10 times higher chip density for data-center-class designs. TSMC has positioned A16 specifically for high-performance computing products that combine complex signal routing with dense power delivery needs, which is a direct description of modern AI accelerators.

On timing, TSMC's original 2024 guidance put A16 production in the second half of 2026. Trade coverage through 2026 has pointed to a production ramp around the fourth quarter of the year, with the first commercial chips built on A16 expected to reach customers sometime after that, likely stretching into 2027. As of this writing, no A16 chip has shipped to end customers; the node itself is further back in its production ramp than Intel's 18A.

How the Two Approaches Differ

Both PowerVia and Super Power Rail solve the same basic problem the same basic way: thin the wafer, connect through nano-scale vias, and give power its own dedicated layers on the back of the die. The two companies differ mainly in timing and in exactly how deep into the transistor the backside connection reaches, with chip-design trade publications generally describing TSMC's approach as connecting closer to the transistor's own source and drain contacts, a more direct but harder-to-manufacture route than tapping in further up the standard cell. Independent, chip-level performance comparisons between the two aren't publicly available yet, since no product built on A16 has shipped, so that distinction remains more of an engineering talking point than a measured result for now.

What is measurable is the calendar: Intel brought a shipping, high-volume backside-power chip to market first, through Panther Lake and Clearwater Forest on 18A. TSMC, which supplies the majority of the industry's leading-edge AI and smartphone chips, is aiming to close that gap with A16 later in 2026 and into 2027.

Why This Matters for AI-Era Chips

Backside power delivery shows up as a footnote in a process-node spec sheet, but the reason both Intel and TSMC prioritized it now is squarely about the demands of modern AI hardware. AI accelerators and the server CPUs that feed them pack enormous numbers of transistors into a single die, run at high sustained power draw for long stretches, and increasingly rely on dense 3D chip stacking, where multiple dies are bonded on top of each other. All three of those trends make the old approach of cramming power and signal wiring into the same front-side metal stack progressively harder to sustain.

Lower resistance in the power-delivery path means less energy wasted as heat before it ever reaches a transistor, which matters directly for performance-per-watt in power-hungry AI training and inference silicon. Freed-up front-side routing room gives chip designers more flexibility to pack in the signal wiring that increasingly complex AI accelerator designs need. And a cleaner separation between power and signal layers is also a more natural fit for the kind of 3D die-stacking that both Intel (through Foveros and 18A-PT) and TSMC (through its own advanced packaging roadmap) are leaning on to keep scaling compute without shrinking transistors indefinitely.

What's Next

The next concrete milestones to watch are straightforward. On Intel's side, 18A-P and 18A-PT are the near-term follow-ons, aimed respectively at further performance-per-watt gains and at backside-power base dies purpose-built for advanced 3D packaging; watch for which future Intel client and server chips adopt them. On TSMC's side, the real test is whether A16 hits its production target later in 2026 and which customers' chips actually ship on it first, since TSMC has pointed to HPC and AI accelerator customers as the node's natural fit. Samsung Foundry has also discussed its own backside power delivery plans for future nodes, though it has not shipped a comparable high-volume product as of October 2026, making Intel and TSMC the two companies actually worth watching in this race for now.

Written byMara Lindqvist

Mara Lindqvist edits the hardware desk. She covers graphics cards, processors, memory and storage, the foundries and chip designers behind them, and what the numbers on a spec sheet mean for people choosing a PC. Specifications in her stories come from manufacturer spec pages and datasheets.

More from Mara LindqvistAll Hardware coverage