Intel Xeon 6+ (Clearwater Forest): Release Date, Specs, and Price

Intel's Xeon 6+ "Clearwater Forest" processors are Intel's first data-center chips built on the 18A process node, and they are already shipping. Intel's own product pages list the family as officially launched in Q2 2026, with four public SKUs ranging from 144 to 288 E-cores, up to 576MB of cache, and recommended customer prices (RCP) running from $4,608 to $14,995 per chip. That answers the three things people keep searching for — release date, specs, and price — straight from Intel's own specification pages, not a leak or a rumor.

What Xeon 6+ Clearwater Forest actually is

Xeon 6+ is the "efficiency-core" branch of Intel's Xeon 6 server lineup, sitting alongside the performance-core Xeon 6 ("Granite Rapids") chips. Clearwater Forest is the internal code name for this specific generation, and it succeeds 2024's Sierra Forest E-core chips. Intel's product pages list the family under the "Intel Xeon 6+ processors" collection, with the code name field explicitly marked "Products formerly Clearwater Forest."

The headline change is the manufacturing process: Clearwater Forest is Intel's first data-center CPU with compute tiles built on Intel 18A, the company's most advanced node and the first to use RibbonFET gate-all-around transistors and PowerVia backside power delivery. Intel talked up Clearwater Forest's 18A debut again at its Computex 2026 keynote, where CEO Lip-Bu Tan and Data Center Group chief Kevork Kechichian presented it as proof that Intel's foundry roadmap is back on schedule.

Release date: already launched, not upcoming

This is the point where a lot of the search traffic goes wrong. Clearwater Forest was previewed at Mobile World Congress in March 2026 and then formally launched around Computex in early June 2026 — not in October, despite some aggregator confusion about timing. Intel's own specification pages for every Xeon 6+ SKU list the launch date as Q2'26 with a marketing status of "Launched." That status field is Intel's own confirmation that the parts are in general availability through server OEMs, not a future roadmap promise.

If you are searching "Intel Clearwater Forest release date" today, the short answer is: it already happened, in the second quarter of 2026, and systems built on it are now shipping from the major server vendors that build on Intel's LGA 7529 platform.

Specs: four SKUs, up to 288 E-cores

Intel's public Xeon 6+ stack currently has four SKUs, all built from E-cores (Intel calls the microarchitecture "Darkmont") with no Hyper-Threading, so thread count matches core count. Every SKU shares the same platform-level support: 12 channels of DDR5-8000 memory, 96 lanes of PCIe Gen 5, up to six Intel Ultra Path Interconnect (UPI) links at 24 GT/s, dual-socket scalability, and a maximum memory capacity of 1.5TB. Each chip also ships with onboard QuickAssist (QAT), Dynamic Load Balancer (DLB), Data Streaming Accelerator (DSA), and In-Memory Analytics Accelerator (IAA) engines, plus Intel TDX and SGX for confidential computing.

Specs and recommended customer prices for all four SKUs come directly from Intel's own product specification pages: 6990E+, 6980E+, 6970E+, and 6960E+.

The flagship 6990E+ doubles the previous Sierra Forest generation's 144-core ceiling, and its 576MB of shared cache works out to a full 2MB per core — a deliberate design choice for cloud-native, microservices-heavy and virtualized-network workloads that spend more time waiting on memory than crunching floating-point math. Every SKU also exposes a second, lower-clocked "SST-PP" (Speed Select Technology — Performance Profile) configuration that trades top frequency for a meaningfully lower TDP, letting operators dial in power versus throughput per rack without buying a different chip.

Why the 18A process node matters here

Clearwater Forest is significant to Intel's business as much as to buyers: it is the first data-center processor shipping on 18A, the node Intel has pitched as the one that proves its foundry can compete with leading-edge external fabs again. Third-party teardown reporting (not confirmed directly by Intel's spec pages) describes a tiled design: up to twelve 24-core compute chiplets fabricated on 18A, sitting above base tiles that handle I/O, memory control and L3 cache on the older Intel 3 node. That disaggregated approach lets Intel put only the parts that most benefit from the new node — the cores themselves — on the expensive, early-yield 18A process, while keeping cache and I/O on a more mature one. Treat the exact tile count and stacking details as credible but unconfirmed by Intel's own public pages, since Intel's specification sheets don't break out the internal packaging.

Clearwater Forest vs. Sierra Forest vs. Granite Rapids

It helps to place Clearwater Forest against the two Xeon 6 generations it sits beside. Sierra Forest, launched in 2024, was Intel's first all-E-core Xeon 6 chip and topped out at 144 cores on the older Intel 3 process; Clearwater Forest doubles that core ceiling to 288 on the newer 18A node while keeping the same no-Hyper-Threading, density-first philosophy. Granite Rapids, meanwhile, is the performance-core (P-core) side of the Xeon 6 family, trading core count for higher per-core clocks and AI-matrix throughput aimed at latency-sensitive and HPC workloads. The two lines share a socket (FCLGA7529) and, at the high end, overlapping price territory — Intel's Xeon 6900P "Granite Rapids" parts have been listed as high as $17,800, versus $14,995 for the Xeon 6+ flagship — but they're built for different jobs. If a workload scales out across many lightweight threads, Clearwater Forest's extra cores and cache-per-core win; if it needs the fastest single thread or heavy AI-matrix math per socket, Granite Rapids is the better fit. Intel's decision to keep selling both lines side by side, rather than consolidating around one microarchitecture, is itself a signal that the company sees E-core and P-core Xeon 6 as separate product strategies rather than a staged replacement.

Pricing: what Intel actually charges

Intel's recommended customer price (RCP) is list pricing for roughly 1,000-unit tray quantities, not a retail price — these chips aren't sold through consumer channels, and actual contract pricing to hyperscalers and OEMs almost always differs. Still, the published numbers give a clear sense of the stack's shape: it roughly doubles in price as core count scales from 144 to 288, with the 6990E+ flagship costing just over 3x the entry 6960E+ for exactly 2x the cores and roughly 33% more cache. That premium buys the higher per-core cache allocation and the extra packaging complexity of the largest die.

For context inside Intel's own catalog, these prices sit below the top-end Xeon 6900P "Granite Rapids" performance-core parts, which Intel has priced as high as $17,800, reflecting the E-core line's positioning as a density-and-efficiency play rather than Intel's single-thread performance flagship.

Platform and memory: same socket, serious I/O

Xeon 6+ drops into the same FCLGA7529 socket as the performance-core Xeon 6 "Granite Rapids" chips, which means OEMs can reuse Granite Rapids-AP board designs for Clearwater Forest deployments rather than engineering a new platform from scratch. Every SKU supports 12 channels of DDR5 at up to 8000 MT/s (one DIMM per channel), 96 lanes of PCIe Gen 5, and up to six UPI 2.0 links for dual-socket scaling — a dual-socket 6990E+ system reaches 576 total E-cores in one server. ECC memory is supported across the line, as expected for a RAS-focused data-center part.

Performance claims: Intel's numbers, not independent benchmarks

Intel has publicly claimed that the 6990E+ delivers roughly 30% higher performance per thread than AMD's 192-core EPYC 9965, along with comparable power-efficiency gains, and that Clearwater Forest overall offers large generational jumps over Sierra Forest in throughput-per-rack and performance-per-watt for telecom and cloud workloads. Telecom equipment maker Ericsson has also been cited presenting internal test results showing double-digit power-efficiency improvements when consolidating from dual-socket Sierra Forest systems to single-socket Clearwater Forest nodes. These are vendor-supplied and vendor-cited figures. No independent, reproducible third-party benchmark suite result for Xeon 6990E+ appears on Intel's own specification pages, so treat the performance comparisons as Intel's marketing claims until independent labs publish their own numbers. Readers who want a vendor-neutral read on recent data-center silicon can compare against MLPerf Inference v6.1 results, which cover a different but related slice of AI hardware benchmarking.

Who Xeon 6+ is actually for

Intel is not pitching Clearwater Forest as a general-purpose server chip. The E-core design trades single-thread peak speed for core density, cache-per-core, and power efficiency, which Intel is aiming squarely at three buyer types: hyperscale cloud operators running scale-out, horizontally-parallel services (web tiers, databases, microservices); telecom operators building virtualized RAN and 5G/6G core-network infrastructure that needs huge numbers of modest-sized packet-processing threads; and, increasingly, "agentic AI" orchestration layers, where a CPU coordinates many lightweight reasoning and tool-calling tasks around GPU-based inference rather than doing the heavy model math itself. None of that overlaps with client or workstation buying decisions, which is also why Xeon 6+ sits apart from Intel's consumer roadmap — for client-side chips and their own 2026 drama, see our coverage of Panther Lake's release and the Nova Lake rumor mill.

Software and ecosystem readiness

A new core microarchitecture and a new process node only matter commercially if the software stack already runs on day one, and server buyers tend to be far more conservative about new silicon than desktop enthusiasts. Intel has pointed to its oneAPI toolkit releases as carrying day-one support for Clearwater Forest alongside its other 2026 silicon, which matters specifically for the compiler and library optimizations (vectorization, threading libraries) that let a 288-core, no-Hyper-Threading chip actually scale across that many independent threads without one core starving another for memory bandwidth. Linux kernel and hypervisor support for the new SST-PP power states and the LGA 7529 platform's RAS (reliability, availability, serviceability) features has also been rolling out through the generations of boards that already support Granite Rapids, which is one practical benefit of Intel reusing the existing socket rather than introducing a new one purely for the E-core line.

What's next

With the four public Xeon 6+ SKUs confirmed as launched and priced, the open questions move to deployment, not specs. Watch for: broader OEM system availability and independent third-party benchmarks that can validate (or puncture) Intel's EPYC comparisons; whether Intel fills out the stack with additional SST-PP configurations or a cheaper entry part below the 6960E+; and how AMD responds on its own next-generation EPYC cloud-native line, since Intel's price-per-core positioning here is explicitly built around beating AMD's current 192-core flagship. We'll update this piece as independent benchmarks and wider retail/OEM pricing become available.

Written byMara Lindqvist

Mara Lindqvist edits the hardware desk. She covers graphics cards, processors, memory and storage, the foundries and chip designers behind them, and what the numbers on a spec sheet mean for people choosing a PC. Specifications in her stories come from manufacturer spec pages and datasheets.

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