Co-Packaged Optics Explained: Why AI Data Centers Need It

Co-packaged optics (CPO) is a chip-packaging approach that puts the optical transmitters and receivers that turn electrical signals into light directly inside the same package as a switch or accelerator chip, instead of plugging them in as separate modules at the edge of a circuit board. For AI data centers, where clusters of GPUs now need to exchange data at hundreds of terabits per second, CPO is the industry's leading answer to a problem pluggable optical transceivers can no longer solve on their own: moving that much data without burning an unsustainable amount of power on driving signals across a board. Nvidia, Broadcom, and TSMC have each put real, named products and manufacturing platforms behind the idea, though the technology is still in its early, first-generation stage of deployment.

What is co-packaged optics?

In a conventional network switch, data travels through the switch chip electrically, then across several centimeters of printed-circuit-board traces to a pluggable optical transceiver module seated at the faceplate, which converts the electrical signal into light for the fiber-optic cable. Co-packaged optics shortens that path by placing the optical engines—the silicon photonics chips that do the electrical-to-optical conversion—on the same substrate or interposer as the switch application-specific integrated circuit (ASIC), inside one package. According to Wikipedia's overview of the technology, this is being developed primarily for data centers, where enormous volumes of data now move between AI accelerators, and it typically relies on silicon photonics components such as microring modulators and integrated photodetectors, since silicon itself does not emit light efficiently and still needs an external laser source.

The result is a much shorter, lower-power electrical interconnect between the switch silicon and the point where the signal becomes light. That is the entire value proposition: CPO does not change what a switch does on the network, it changes how efficiently the chip talks to the fiber.

Why pluggable transceivers are becoming the bottleneck

Pluggable transceivers have been the networking industry's default for decades because they are modular, field-replaceable, and decoupled from the switch chip's design cycle. That modularity, though, has a cost. The electrical signal has to be driven far enough, cleanly enough, to reach the faceplate, which requires power-hungry driver and retimer circuitry and introduces signal-integrity loss along the way. As switch chips have scaled from tens of terabits per second to over 100 terabits per second, and as AI training clusters have grown toward hundreds of thousands or millions of accelerators that all need to talk to each other, the number of optical ports—and the power spent driving signals to each one—has scaled right alongside them.

Broadcom frames this directly on its own co-packaged optics pages: its stated goal for CPO is to cut the power and cost of that electrical-to-optical conversion path by integrating the optics at the package level rather than the board edge. Nvidia makes a similar argument in its own material on Spectrum-X and Quantum-X Photonics, framing CPO as the way to keep scaling what it calls "AI factories"—GPU clusters that may eventually number in the millions of accelerators—without networking power and resiliency becoming the limiting factor. Chip packaging choices like this are part of a broader pattern across the industry of moving functions closer together on a single package to cut interconnect losses, a trend also visible in chiplet-based processor design, where compute tiles are stitched together on a single package rather than communicating across a board.

How CPO actually works

A CPO switch pairs two kinds of silicon in one package: the switch ASIC, which does the packet switching and runs electrically, and one or more optical engines, which are silicon photonics chips built to carry many lanes of light. The two are connected by extremely short, high-density electrical links inside the package rather than board traces, which is what cuts the driver power needed. The optical engines themselves still need external, replaceable laser sources in most current designs, since silicon does not emit light well on its own—so "co-packaged" refers to the optical engine and modulators being integrated with the switch, not necessarily the laser.

Nvidia's SN6800 Spectrum-X Ethernet Photonics switch, described on Nvidia's own developer blog, illustrates the engineering involved: it uses a quad-ASIC architecture with an integrated fiber shuffle, a detachable fiber connector with surface-normal input/output, and solder-reflow-compatible optical engines that Nvidia says are tested before assembly to help ensure yield. These details point to the two hardest problems in CPO: getting enough optical lanes physically connected to a package without pluggable connectors, and manufacturing optical engines reliably enough that a single bad one doesn't force a switch to be scrapped.

Nvidia's Spectrum-X Photonics and Quantum-X Photonics

Nvidia announced its first co-packaged optics switch lines—Spectrum-X Photonics for Ethernet and Quantum-X Photonics for InfiniBand—in a newsroom announcement timed to GTC, positioning them as infrastructure for scaling "AI factories" to millions of GPUs. The Quantum-X Photonics InfiniBand switch is specified at 144 ports of 800Gb/s, based on 200Gb/s SerDes lanes, and uses a liquid-cooled design to manage heat from the onboard silicon photonics. The Spectrum-X Photonics Ethernet line comes in multiple configurations, including one with 512 ports of 800Gb/s (or 2,048 ports of 200Gb/s) for roughly 400Tb/s of total switch bandwidth; Nvidia's developer blog gives the more precise figure of 409.6 Tb/s for its SN6800 Ethernet Photonics switch, which it describes as the flagship networking switch for its Rubin GPU platform—the same platform covered in Pandromeda's explainer on Nvidia's Vera Rubin release.

Nvidia's own comparisons, versus its traditional pluggable-optics switches, claim 4x fewer lasers, 3.5x better power efficiency, 63x greater signal integrity, 10x better network resiliency at scale, and 1.3x faster deployment for the photonics line. The company's newsroom material also states that Quantum-X Photonics InfiniBand switches were expected to become available later in 2025, with Spectrum-X Photonics Ethernet switches following in 2026 from infrastructure and system vendor partners. Nvidia named a broad manufacturing ecosystem behind the launch, including TSMC, Coherent, Corning, Foxconn, Lumentum, and SENKO as collaborators on the underlying inventions, alongside additional ecosystem partners such as Browave, Fabrinet, SPIL, Sumitomo Electric, and TFC Communication.

Nvidia CEO Jensen Huang framed the shift in blunt terms in the company's announcement: "AI factories are a new class of data centers with extreme scale," and, on the engineering approach, "By integrating silicon photonics directly into switches, NVIDIA is shattering the old limitations." TSMC chairman and CEO C.C. Wei was quoted in the same release saying that "a new wave of AI factories requires efficiency and minimal maintenance to achieve the scale required"—a line that points directly at TSMC's own manufacturing role, covered below.

Broadcom's Bailly, Davisson, and the Tomahawk CPO roadmap

Broadcom has pursued co-packaged optics across multiple generations of its Tomahawk Ethernet switch family, and names its CPO switches after its internal codenames: Tomahawk 5–Bailly was Broadcom's earlier-generation CPO Ethernet switch, and Tomahawk 6–Davisson is its newer one, which Broadcom describes as the industry's first 102.4-Tbps Ethernet switch with co-packaged optics—double the bandwidth of the Bailly generation. Broadcom's own co-packaged optics product page states platform-level claims for its CPO technology as a whole: greater than 3.5x power consumption savings, 40% lower optics cost per bit, and more than 1 Tbps per millimeter of bandwidth density, all attributed to placing optics next to the switch ASIC on a shared packaging substrate rather than routing signals out to board-edge pluggables.

Broadcom's CPO work sits alongside its broader Tomahawk 6 switch family, which the company says is already shipping in production volume as of its March 2026 announcement. Asad Khamisy, Broadcom's senior vice president and general manager of its Core Switching Group, said in that announcement that "Tomahawk 6 doubles the throughput of its predecessor Tomahawk 5" and highlighted that Broadcom took the chip "to production in less than three quarters from initial sampling." Independent analysts quoted in the same release underscored the networking case for fewer, more powerful switch tiers: Bob Wheeler of LightCounting noted that "for AI scale-up networks, a single Tomahawk 6 can connect 512 XPUs," adding that "fewer tiers mean lower latency, simpler load balancing and congestion control, and fewer optics." Broadcom has also said it is working with Tencent to accelerate commercialization of a CPO-based network switch, part of a stated ecosystem that includes Corning, Foxconn, SPIL, Juniper, Micas, H3C, Ruijie, and Delta.

TSMC's COUPE: the manufacturing platform behind the optics

Both Nvidia's and Broadcom's co-packaged optics switches depend on a manufacturing step that sits upstream of either company: fabricating and packaging the silicon photonics dies themselves. TSMC's platform for this is called COUPE, the Compact Universal Photonic Engine, which TSMC has confirmed by name in its own technology symposium material as a silicon photonics integration offering positioned alongside its logic process roadmap for high-performance computing. Nvidia listed TSMC among its named collaborators on the "joint inventions" behind Spectrum-X and Quantum-X Photonics, and industry reporting has described COUPE as combining an electronic die with a photonic die using TSMC's chip-stacking packaging techniques—though TSMC's own public pages available at the time of writing give fewer specifics on exact power or bandwidth figures for COUPE than Nvidia and Broadcom publish for their own finished switches, so those more granular manufacturing-level claims should be treated as less firmly confirmed than the switch-level figures above.

What is clear from TSMC's own material is that COUPE is a real, named, trademarked platform the company is building out specifically to support silicon photonics customers—placing TSMC in a similar foundational role for CPO that it already plays in advanced chip packaging more broadly, a role discussed in Pandromeda's explainer on chiplet design and in coverage of TSMC's logic roadmap in the N2 process explainer. Just as TSMC's advanced packaging lines became the bottleneck and enabler for chiplet-based processors, its photonics packaging capacity is shaping up to be a similar chokepoint for how quickly CPO switches can scale from early shipments to broad availability.

The challenges: yield, repairability, and supply chain

Wikipedia's technical overview of co-packaged optics lists the main obstacles the industry is still working through, and they line up with what Nvidia and Broadcom have each tried to engineer around: manufacturing yield for the optical engines themselves, limited silicon-photonics production capacity, competition for the same advanced-packaging capacity used by other high-end chips, heat dissipation at high power density, the difficulty of coupling optical fiber to very narrow silicon waveguides, and serviceability—since a failed optical port that is built into the switch package is far harder to replace than unplugging a bad transceiver module.

Nvidia's SN6800 design addresses the serviceability and yield questions directly, with Nvidia's developer blog describing solder-reflow-compatible optical engines that are tested before final assembly specifically to catch defects early, plus a detachable fiber connector so that fiber, at least, isn't permanently fused to the package. Broadcom's emphasis on "best-in-class reliability" and its claim of already "shipping production CPO systems today" on its own CPO product page reflects the same underlying concern: CPO only makes sense for data center operators if it is at least as reliable in the field as the pluggable transceivers it replaces, not merely more power-efficient on paper.

Where CPO fits in the AI data center stack

CPO is not a replacement for every optical link in a data center today—it is, so far, concentrated in the highest-bandwidth switch tiers of the largest AI clusters, where the power cost of thousands of pluggable transceivers becomes significant enough to justify a less field-serviceable, more tightly integrated alternative. Nvidia's Quantum-X Photonics and Spectrum-X Photonics switches are explicitly marketed as scale-out and scale-up networking for GPU clusters, not general-purpose enterprise networking. Broadcom's Tomahawk 6–Davisson line is aimed at the same category of hyperscale AI fabric, where a single switch can connect hundreds of accelerators in one hop and where cutting switch tiers—and the optics that go with each tier—has a direct effect on both latency and total cost.

That positioning explains why CPO adoption is tracking closely with the broader AI infrastructure buildout rather than general networking refresh cycles. As GPU platforms scale—a dynamic also visible in memory technology, where HBM4 bandwidth increases are pushed by the same AI accelerator demand—the networking layer connecting those accelerators has become a parallel bottleneck that CPO is specifically designed to loosen.

What next for co-packaged optics

Based on what Nvidia and Broadcom have stated publicly, the near-term trajectory is incremental rather than a sudden industry-wide switch: Nvidia's Quantum-X Photonics InfiniBand switches were targeted for availability in 2025, with Spectrum-X Photonics Ethernet switches following through 2026 via infrastructure and system vendor partners, while Broadcom has already moved from its first-generation Tomahawk 5–Bailly CPO switch to the higher-bandwidth Tomahawk 6–Davisson generation and describes its overall Tomahawk 6 switch family as shipping in production volume. TSMC's COUPE platform is the manufacturing layer both companies are depending on to keep scaling optical engine output, which means TSMC's packaging capacity—much like its advanced logic and CoWoS packaging capacity for AI accelerators—is likely to be a recurring supply-chain story alongside GPU and switch chip availability itself. For readers tracking AI infrastructure, the practical signal to watch is less about any single power-efficiency percentage and more about whether CPO switches move from named, limited early deployments into the default networking layer for the largest AI training and inference clusters.

Written byMara Lindqvist

Mara Lindqvist edits the hardware desk. She covers graphics cards, processors, memory and storage, the foundries and chip designers behind them, and what the numbers on a spec sheet mean for people choosing a PC. Specifications in her stories come from manufacturer spec pages and datasheets.

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