Intel Diamond Rapids Explained: What We Know So Far

Intel Diamond Rapids is the codename for Intel's next-generation Xeon server processor, confirmed by Intel itself to be built on the Intel 18A-P manufacturing process and to scale up to 256 new cores with 1.28 GB of last-level cache, 16 memory channels, and 128 lanes of PCIe Gen 6 plus CXL 3.0. It succeeds Intel's current Xeon 6 generation and is positioned for enterprise data center and cloud workloads, particularly "agentic AI" orchestration. Intel has not yet published a release date, final core counts for shipping SKUs, clock speeds, or pricing — those remain unconfirmed. Oracle has already named Diamond Rapids as the planned foundation for a future Oracle Cloud Infrastructure (OCI) compute generation, making it the chip's first publicly confirmed customer commitment.

What is Intel Diamond Rapids?

Diamond Rapids is the internal codename Intel uses for its next full-generation Xeon server CPU, the chip that will eventually succeed the Xeon 6 family in Intel's data center lineup. Intel's own description, published in its August 24, 2026 newsroom post covering its Hot Chips 2026 presentation, introduces it as "the Diamond Rapids processor for high-performance orchestration," and later refers to it directly as "the next gen Xeon codenamed Diamond Rapids."

That same newsroom post is the most detailed official source available on the chip to date. Intel presented Diamond Rapids alongside two other pieces of silicon — an inference-focused data center GPU codenamed Crescent Island, and a client/edge chip codenamed Wildcat Lake — as part of what it frames as a three-tier hardware strategy for agentic AI, with Diamond Rapids handling the CPU-side orchestration layer.

One naming note worth flagging: Diamond Rapids is widely referred to across the industry, and in Intel's own product roadmap slides at events like Computex, as "Xeon 7," the implied successor branding to today's Xeon 6 line. Intel's Hot Chips 2026 newsroom copy itself, however, does not use that brand name — it refers to the chip only by its codename. Until Intel formally brands it in an ARK listing or a product launch release, "Xeon 7" should be treated as the expected, but not yet newsroom-confirmed, marketing name.

The process node and packaging Intel has confirmed

According to Intel's newsroom post, Diamond Rapids is "built exclusively on Intel technology, including the power- and performance-enhanced Intel 18A-P" process. Intel describes the broader architecture as "underpinned by Intel Foundry technologies including the Intel 18A process family," combining "adaptable compute building blocks, a unified memory fabric, and flexible I/O."

On packaging, Intel confirms "advanced SoC construction using Foveros Direct 3D and UCIe-S interconnect" — meaning Diamond Rapids is a multi-die, chiplet-based design rather than a single monolithic chip, using Intel's hybrid-bonding 3D stacking technology together with the open Universal Chiplet Interconnect Express standard for die-to-die communication. Intel also lists a "high-bandwidth memory subsystem," new Advanced Performance Extensions (APX) intended to cut instruction overhead, and an enhanced version of Advanced Matrix Extensions (AMX) for AI workloads.

18A-P is a performance-enhanced derivative of the same Intel 18A node that already underpins Intel's current Xeon 6+ generation, codenamed Clearwater Forest — the E-core Xeon 6+ lineup Intel has already brought to market. In other words, Diamond Rapids isn't introducing a brand-new node to Intel's data center roadmap so much as pushing an existing one further.

Core counts and cache: what Intel has actually said

The single most-quoted figure from Intel's own materials is this line from the Hot Chips 2026 newsroom post: Diamond Rapids offers "up to 256 new cores with 1.28 GB LLC." That "up to" phrasing matters — it describes a maximum configuration Intel has disclosed, not a confirmed, finalized SKU stack. Intel has not published a model-by-model core count breakdown, base or turbo clock speeds, per-SKU power envelopes, or pricing for Diamond Rapids. Any of those details circulating elsewhere should be treated as unofficial until Intel issues a product-level launch release or an ARK listing.

On the platform side, Intel's confirmed figures are more specific:

• Memory: 16 memory channels, running at up to 12,800 MT/s
• I/O: 128 lanes of PCIe Gen 6
• Interconnect/expansion: CXL 3.0 support

Those platform-level numbers — channel count, I/O lane count, and the CXL generation — come directly from Intel's own newsroom disclosure rather than from leaked roadmap slides, which is why this article treats them as confirmed while treating exact core counts per SKU, clocks, and launch timing as still open questions.

Target market: why Diamond Rapids is built around agentic AI

Intel is not positioning Diamond Rapids primarily as a general-purpose core-count race against AMD, at least not in its own messaging. Its newsroom post describes the chip as "a versatile processor designed for enterprise-scale Agentic AI," built for "high-performance orchestration," with Intel emphasizing "consistent high performance, efficiency and scalability" as the chip's core value proposition.

That framing lines up with how Intel grouped Diamond Rapids alongside Crescent Island and Wildcat Lake at Hot Chips 2026: a CPU for coordinating complex, multi-step AI agent workflows and running the application logic around them; a GPU for sustained, heavier inference; and a client SoC for keeping some AI tasks local to the device. In that split, Diamond Rapids' job in a data center is less about running the largest models directly and more about orchestration — routing requests, managing context, running the software layer that AI agents depend on — while still carrying meaningfully upgraded AI-adjacent instructions (enhanced AMX, new APX) on-die.

The Oracle OCI deal: Diamond Rapids' first confirmed customer

On October 27, 2026, at Oracle AI World in Las Vegas, Intel and Oracle jointly announced what both companies describe as a "planned multiyear collaboration" to support enterprise and agentic AI on Oracle Cloud Infrastructure. The release is the clearest public signal that Diamond Rapids has a named commercial destination, even though neither company has committed to shipping dates.

Specifically, Oracle's planned next-generation compute shapes — referred to as OCI X14 — are described as "expected to be based on" Intel's "next-generation server processor codenamed Diamond Rapids." The companies say these planned systems are expected to bring an enhanced AMX implementation with FP8, FP16, and BF16 support for inference software, plus Intel's APX extensions to help optimized applications run with less instruction overhead. The target workloads named in the release are squarely AI-infrastructure focused: embedding generation, reranking, and smaller-model inference, alongside the broader application services that AI agents rely on. You can read more about the deal's scope in Pandromeda's earlier coverage of Intel and Oracle's planned Diamond Rapids expansion on OCI.

Two important caveats come straight from the release itself. First, it covers "current and future Xeon platforms" broadly, not Diamond Rapids exclusively — Diamond Rapids is the processor OCI X14 specifically is expected to use. Second, Oracle's press release carries an explicit forward-looking statement disclaimer: the product directions described are "not a commitment to deliver any material, code, or functionality," should not be relied on for purchasing decisions, and remain subject to change at Oracle's discretion. Both companies also say they "intend to coordinate roadmaps and processor capacity planning" as OCI expands, but no financial terms, unit volumes, or dates were disclosed.

Release timing: what's confirmed and what's still unconfirmed

Neither of Intel's two most relevant official statements on Diamond Rapids — the August 24, 2026 Hot Chips newsroom post and the October 27, 2026 Oracle collaboration release — includes a release date. The Hot Chips post frames Diamond Rapids as something Intel "will discuss" at the event, consistent with a technical architecture preview rather than a product launch, and it gives no shipping window. The Oracle release likewise describes OCI X14 only as "planned" and "expected," with timing explicitly left open and subject to Oracle's own disclosure terms.

That means, as of this writing, there is no Intel-confirmed release date for Diamond Rapids. Launch-year estimates circulating in trade coverage and roadmap leaks are not sourced to an Intel newsroom release or ARK listing, so this piece treats them as TBA rather than fact. What is confirmed is the sequencing: Diamond Rapids is explicitly described by Intel as the "next gen Xeon," meaning it follows — rather than replaces concurrently — the current Xeon 6 generation already shipping today.

How Diamond Rapids fits the current Xeon lineup

Intel's current data center lineup is built around Xeon 6, split between P-core SKUs aimed at per-core performance and the E-core Xeon 6+ "Clearwater Forest" family aimed at core-density and efficiency, both manufactured on members of the Intel 18A process family. Diamond Rapids is Intel's description of what comes after that generation — the next full Xeon architecture, rather than a mid-cycle refresh of Xeon 6.

The table below lines up what's officially confirmed for Diamond Rapids against Clearwater Forest (already shipping) and AMD's rival EPYC "Venice" platform (also already launched), using only figures traceable to Intel's own newsroom disclosures or encyclopedia reference entries. Anything Intel or AMD has not disclosed is marked TBA rather than estimated.

The practical takeaway: both of Diamond Rapids' direct rivals in this table — Intel's own current-generation Xeon 6+ and AMD's EPYC Venice — have already reached the market, while Diamond Rapids itself remains at the architecture-preview stage. That's not unusual for how Intel has historically disclosed Xeon generations (detailed technical previews well ahead of launch), but it does mean side-by-side spec comparisons right now are necessarily comparing a shipping product to a disclosed-but-unreleased one.

Diamond Rapids vs. AMD EPYC Venice, in brief

AMD's Zen 6-based EPYC "Venice" (the 9006 series) launched on July 23, 2026, built on TSMC's N2 process and described in encyclopedia references as the first high-performance x86 CPU manufactured on a 2 nm-class node, spanning 8 to 256 cores per socket on a new SP7 platform. That gives AMD a shipping, 2 nm-class, up-to-256-core server platform in market months before Intel has even set a date for Diamond Rapids.

That timing gap is the headline, but it's not the whole story — core counts, packaging philosophy, memory architecture, and target workloads differ in ways that a single spec row can't capture. For a fuller breakdown of exactly which Diamond Rapids and EPYC Venice claims are Intel/AMD-confirmed versus rumored, see Pandromeda's dedicated comparison: Intel Diamond Rapids vs. AMD EPYC Venice, what's actually confirmed.

What's next for Diamond Rapids

With Diamond Rapids still at the architecture-preview stage, three things are worth watching for next. First, a formal product launch release or ARK listing from Intel, which would convert the current "up to 256 cores" ceiling into an actual SKU stack with clock speeds, power envelopes, and pricing. Second, further detail on Oracle's planned OCI X14 shapes, including any availability timing Oracle attaches once its own forward-looking disclaimers lift. Third, additional partner announcements beyond Oracle — Diamond Rapids' positioning around agentic AI orchestration makes it a likely subject of further cloud-provider commitments before it ships.

Until Intel publishes that next layer of official detail, the safest summary is the one this piece has tried to stick to: Diamond Rapids is a confirmed next-generation Xeon, built on Intel 18A-P, disclosed at up to 256 new cores with 1.28 GB of cache, 16 memory channels, and 128 lanes of PCIe Gen 6 with CXL 3.0, aimed at enterprise agentic AI workloads and already tied to Oracle's cloud roadmap — with everything else, including the exact release date, still TBA.

Written byMara Lindqvist

Mara Lindqvist edits the hardware desk. She covers graphics cards, processors, memory and storage, the foundries and chip designers behind them, and what the numbers on a spec sheet mean for people choosing a PC. Specifications in her stories come from manufacturer spec pages and datasheets.

More from Mara LindqvistAll Hardware coverage